The present invention generally relates to master slice type integrated circuits, and in particular to a master slice type integrated circuit which comprises a plurality of basic cells and a plurality of input/output cells which are pre-formed.
A master slice type integrated circuit has been widely researched and manufactured. A complementary metal oxide semiconductor (CMOS) gate array is an example of applications of the master slice type integrated circuit. The master slice type integrated circuit comprises a semiconductor chip on which there are formed basic cells arrayed like a matrix and input/output cells arranged in a peripheral region on the chip outside a region in which the basic cell matrix is formed. Generally, each basic cell comprises a plurality of transistors. Pre-processing for forming transistors except for interconnection metallizations is commonly carried out. At an interconnecting step which is a last step of steps for producing the master slice type integrated circuit, arbitrary routing of interconnection lines may be selected. Therefore, desired logic circuits can be constituted by interconnecting the basic cells and I/O cells in accordance with the user's requests.
The input/output cells (hereafter simply referred to as I/O cells) are used to supply the logic circuits on the chip with signals which are provided by an external circuit and to feed output signals of the logic circuits to the external circuit. Interconnections to build circuits of the I/O cell may be also arbitrarily made in accordance with a user's specification. Generally, the interconnection between the I/O cell circuits is made by use of a first (lower) layer metallization deposited on an insulator on a silicon crystal of the chip, and power supply lines are made by a second (upper) layer metallization.
In a practical use of the master slice type integrated circuit, a plurality of circuit blocks are constituted by coupling basic cells with one another by interconnecting lines. These circuit blocks are connected to one another by a data bus, so that signal transmission amoung the circuit blocks may be made. In this structure, an input buffer and an output buffer are interposed between each circuit block and the data bus. The input and output buffers are made up of basic cells in the matrix. Further, a latch circuit is connected to the data bus. The latch circuit has a function of preventing the data bus from being changed into a floating state, when all of the output buffers coupled with the data bus are changed into a high-impedance state. In other words, the latch circuit has a function of keeping the potential of the data bus to prevent the bus from being changed into a floating state. When the data bus is kept in the floating state, there is a risk that the circuit blocks malfunction.
Generally, the latch circuit is made up of an input inverter and an output inverter which are connected to each other in a state where the output terminal of one inverter is connected to the input terminal of the other. The input terminal of the input inverter is coupled with the data bus, and the output terminal of the output inverter is also coupled with the data bus. The input and output inverters are constituted by use of basic cells.
However, the conventional master slice type integrated circuit has the following disadvantages resulting from the latch circuit constituted by the basic cells. Firstly, the latch circuit connected to the data bus may distort a waveform of a data signal and thereby causes a time delay of the data signal. This becomes greater as a driving capability of the latch circuit is increased. As described before, the latch circuit is made up of the basic cells. For this reason, there is a possibility that it becomes impossible to optimize the driving capability of the latch circuit with respect to the data bus. This holds true for a case that a driving capability of one basic cell is greater than a load on the data bus. In this case, it is impossible to match the driving capability of the latch circuit with the data bus, because the latch circuit having a driving capability smaller than that of the basic cell is not available. Hence, the distortion of the waveform of the data signal is increased and thereby the time delay of the data is also increased. It should be noted that the latch circuit is used to keep the potential of the data bus stable and constant. This means that it is not necessary to have a large driving capability. In particular, the driving capability of the input inverter of the latch circuit may be made smaller than that of the output inverter thereof.
Secondly, the output buffers interposed between the respective circuit blocks and the data bus must have a driving capability exceeding a load on the data bus with which a plurality of circuit elements are coupled. In this case, the presence of the latch circuit having the relatively large driving capability increases the load on the data bus. For this reason, each of the output buffers must be constituted by a number of basic cells. This also leads to the reduction of usable basic cells to build logic circuits.